R1100 rdc ? risc dsp communication 16 bit risc micro processor specifications subject to change without notice, contact your sales representatives for the most update information. rdc confidential page 1 of 5 rev 1.0 may. 04 2007 R1100 brief sheet 16 bit risc micro processor
R1100 rdc ? risc dsp communication 16 bit risc micro processor specifications subject to change without notice, contact your sales representatives for the most update information. rdc confidential page 2 of 5 rev 1.0 may. 04 2007 1 features l cpu core - rdc s proprietary risc architecture - five-stages pipeline - operation frequency: 80mhz - support cpu id - supports 32 pio pins - external bus, internal bus and core in the same clock base l bus interface - multiplexed address and data bus - with 8-bit or 16-bit boot rom bus size - supports direct address bus [a19 : a0] - 8-bit or 16-bit external bus dynamic access l rom/ram/dram controller and addressing space - 1m byte memory address space - 64k byte i/o space l software - software compatible with generic 80c186 microprocessor l asynchronous serial channels - support two asynchronous serial channels with hardware handshaking signals. l interrupt controller - the interrupt controller with seven maskable external interrupts and one non-maskable external interrupt (nmi) l two independent dma channels l integrate pll(*1~*8) l programmable chip-select logic - programmable chip-select logic for memory or i/o bus cycle decoder l programmable wait-state generator l counter/timers - three independent 16-bit timers and one independent programmable watchdog timer l operating voltage range - operation voltage: 3.3v - i/o pin input voltage: 3.3v ~ 5v - i/o pin output voltage: 3.3v l package type - 100 pin pqfp & lqfp l a green product
rdc ? risc dsp communication R1100 16 bit risc micro processor specifications subject to change without notice, contact your sales representatives for the most update information. rdc confidential page 3 of 5 rev 1.0 may. 04 2007 2. block diagram dma unit psram control unit chip select unit refresh control unit bus interface unit pio unit synchronous serial interface timer control unit interrupt control unit clock & power management asynchro- nous serial port instruction queue (64bits) instruction decoder register file general, segment, eflag register alu (special, logic, adder, bsf) micro rom ea / la address control signal execution unit x1 x2 clkouta clkoutb int4 int0 tmrin0 tmrout0 tmrin1 tmrout1 drq0 drq1 txd rxd sclk sden0sden1 sdata a19~a0 ad15~ad0 ale bhe/aden wr wlb whb rd vcc gnd lcs/once0 mcs3/rfsh ucs/once1 pcs5/a1 pcs6/a2 ardy srdy s2~s0 dt/r den hold hlda s6/clkdiv2 uzi int3/inta1/irq int2/inta0 int1/select nmi rst mcs2-mcs0 pcs3-pcs0 pll
rdc ? risc dsp communication R1100 16 bit risc micro processor specifications subject to change without notice, contact your sales representatives for the most update information. rdc confidential page 4 of 5 rev 1.0 may. 04 2007 3. package information 100 pin pqfp 0.089 c seating plane 0.25 min a1 0.22/0.38 b1 b 0.22/0.30/0.33 0.13/0.23 0.13/0.17 c1 c with plating base metal "a" d1 20.00 0.10 d 23.20 0.25 e1 14.00 0.10 e 17.20 0.25 "a" 0.65 bsc 0~7 1.60 ref 0.25 0.88 0.15 l l1 a2 2.75 0.12 detail a 3.40 max 7 typ 15 typ detail a
rdc ? risc dsp communication R1100 16 bit risc micro processor specifications subject to change without notice, contact your sales representatives for the most update information. rdc confidential page 5 of 5 rev 1.0 may. 04 2007 100 pin lqfp sealing plane 1 25 26 50 51 75 76 100 0.127(typ) "a" 0.076(max) 0.50(typ) 1.60(max) 1.00(ref) 0.2s(typ) gauge plane 16.00 0.10 14.00 0.10 16.00 0.10 14.00 0.10 1.40 0.05 0.10 0.05 0.22 0.05 0.60 0.15 0 ~ 7 unit:mm
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